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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Features
* * * Using external 32.768kHz quartz crystal Supports I2C-Bus's high speed mode (400 kHz) Includes time (Hour/Minute/Second) and calendar (Year/Month/Date/Day) counter functions (BCD code) * * * * Programmable square wave output signal Oscillator stop flag Low backup current: typ. 500nA at VDD=3.0V and TA=25C Operating range: 1.8V to 5.5V
Description
The PT7C4363 serial real-time clock is a low-power clock/calendar with a programmable square-wave output.
Address and data are transferred serially via a 2-wire bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in the 24hour format indicator. Table 1 shows the basic functions of PT7C4363. More
Ordering Information
Part Number PT7C4363P PT7C4363W Package 8-Pin DIP 8-Pin SOIC
details are shown in section: overview of functions.
Note: Lead free package is available by adding "E" after each part number. For example: PT7C4363PE. Table 1. Basic functions of PT7C4363 Item Function Source: Crystal: 32.768kHz 1 Oscillator Oscillator enable/disable Oscillator fail detect Time display 2 Time Century bit Time count chain enable/disable 3 4 5 Interrupt Alarm interrupt Timer interrupt output 2-wire I2C bus 3-wire bus Burst mode Write protection External clock test mode Power-on reset override 12-hour 24-hour
PT7C4363 1, 32, 1.024k, 32.768k
Programmable square wave output (Hz) Communicat ion
6
Control
PT0207(07/05) 1
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Function Block
PT7C4363
X1
32.768 kHz
CD
Comparator
Alarm Register
(Min, Hour, Day, Date)
OSC
Counter Chain
Timer
Time Counter
(Sec,Min,Hour,Day,Date,Month,Year)
X2
CG
Control Register
Address Decoder
Address Register I /O Interface (I2C) Shift Register
SCL
INT SQW
Timer / Alarm Interrupt Control Square Wave Output Control
SDA
Note: PT7C4363 need to add a 10pF ~ 30pF capacitor between X1 and GND to get the accurate 32k frequency.
Recommended Layout for Crystal
PT7C4363 PT7C4307
Local Ground plane Layer 2 Guard Ring (connect to gound)
Crystal Specifications
Parameter Nominal Frequency Series Resistance Load Capacitance Symbol fO ESR CL Min Typ 32.768 10 Max 40 Unit kHz k pF
The crystal, traces and crystal input pins should be isolated from RF generating signals.
PT0207(07/05) 2
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Pin Configuration
PT7C4363
1
X1
VCC
8
2
X2 INT
SQW 7 SCL
6
3
4
GND
SDA
5
DIP-8 SOIC-8
Pin Description
Pin no. 1 Pin X1 Type I Description Oscillator Circuit Input. Together with X2, 32.768kHz crystal is connected between them.
2
X2
O
Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them.
3
INT
O
Interrupt Output. Open drain, active low.
4
GND
P
Ground. Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pull-up resistor. Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. Clock Output. Open drain. Four frequencies selectable: 32.768k, 1.024k, 32, 1Hz when SQWE bit is set to 1. Power.
5 6 7
SDA SCL SQW
I/O I O
8
VCC
P
PT0207(07/05) 3
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Function Description
Overview of Functions
1.
Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.
2.
Alarm function
These devices have one alarm system that outputs interrupt signals from INTA for PT7C4363 or INT/OUT/SQW for PT7C4341 to CPU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a specified time. The alarm may be selectable between on and off for matching alarm or repeating alarm.
3.
Programmable square wave output
A square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 32, 1.024k, 32.768k Hz.
4.
Interface with CPU
Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is also open drain. The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode.
5.
Oscillator fail detect
When oscillator fail, OSF bit will be set.
6.
Oscillator enable/disable
Only time count chain can be enable or disable by STOP bit..
7.
Timer function
The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 1/60 Hz) and enables or disables the timer. The timer counts down from software loaded 8-bit binary value. At the end of every countdown, the timer sets the Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt. The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. Bit TI/TP is used to control this mode selection. When reading the timer, the current countdown value is returned.
8.
Reset function
The PT7C4363 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I2C-bus logic is initialized and all registers, including the address pointer, are cleared with the exception of bits FE, OSF, TD1, TD0, TESTC and AE which are set to logic 1.
PT0207(07/05) 4
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Registers
1. Allocation of registers Function (time range BCD format) Control/status 1 Control/status 2 Seconds (00-59) Minutes (00-59) Hours (00-23) Dates (01-31) Days of the week (00-06) Months (01-12) Years (00-99) Alarm: Minutes (00-59) Alarm: Hours (01-12) Alarm: Dates (01-31) Alarm: Weekday (00-06) SQW control Timer control Timer Register definition Bit 7 TEST1*
2
Addr. (hex) *1 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
Bit 6 S40 M40 x x x x Y40 M40 x x x x x
Bit 5 STOP*3 S20 M20 H20 D20 x x Y20 M20 H20 D20 x x x
Bit 4 TI/TP*5 S10 M10 H10 D10 x MO10 Y10 M10 H10 D10 x x x
Bit 3 TESTC*4 AF*6 S8 M8 H8 D8 x MO8 Y8 M8 H8 D8 x x x
Bit 2 TF*6 S4 M4 H4 D4 W4 MO4 Y4 M4 H4 D4 W4 x x
Bit 1 AIE*7 S2 M2 H2 D2 W2 MO2 Y2 M2 H2 D2 W2 RS1 TD1*11
Bit 0 TIE*7 S1 M1 H1 D1 W1 MO1 Y1 M1 H1 D1 W1 RS0 TD0*11
OSF*8 x x x x Century Y80 AE*9 AE*9 AE*9 AE*9 SQWE TE*10
Timer count down value
Caution points: *1. PT7C4363 uses 8 bits for address. For excess 0FH address, PT7C4363 will not respond. *2. EXT_CLK test mode select bit. *3. When the bit is logic 1, time count chain stops but oscillator still runs. *4. Power-on reset override enable bit. *5. Timer interrupt output select bit. *6. Alarm and timer interrupt flag bits. *7. Alarm and timer interrupt enable bits. *8. Oscillator fail indicates. Indicate clock integrity. *9. Alarm enable bit. Alarm will be active when related time is matching if AE = 0. *10. Timer enable bit. *11. Timer source clock frequency select. *12. All bits marked with "x" are not implemented. All bits marked with "-" are not used bits and should always be written with logic 0. If read them, they could be logic 0 or 1.
PT0207(07/05) 5
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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2.
Control and status register
Addr. (hex) 00 01 0D 0E 0F
Description Control/status 1 (default) Control/status 2 (default) SQW control (default) Timer control (default) Timer (default)
D7 TEST1 0
D6 Undefined
D5 STOP 0
D4 Undefined TI/TP 0
D3 TESTC 1
D2
D1
D0
Undefined Undefined Undefined AIE 0 RS1 0 TD1 1 TIE 0 RS0 0 TD0 1
Undefined Undefined Undefined SQWE 1 TE 0
AF TF Undefined Undefined
x x x x x Undefined Undefined Undefined Undefined Undefined x x x x x Undefined Undefined Undefined Undefined Undefined Timer count down value Undefined
a) *
Timer TE: Timer Enable bit. TE Data 0 Read / Write 1 Timer enabled Timer disabled
Description Default
*
TD1, TD0: timer source clock frequency select. These bits determine the source clock for the countdown timer. TD1, TD0 Data Timer source clock freq. (Hz) 00 01 Read / Write 10 11 1 1/60 When not in use, TD1 TD0 should be set to 11 for power saving. 4.096k 64
*
Timer: Timer Read / Write
Data 00~FF Count down value (n)
Description Countdown Period = n / Source Clock Frequency
For example: If TE = 1, TD1 TD0 = 10, Timer = 03 are written into PT7C4363, timer counts down every 1 second from 03 to 01 then 03 cycled.
PT0207(07/05) 6
Ver: 0
Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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b) *
Timer Interrupt TIE: Timer Interrupt Enable bit. TIE Data 0 Read / Write 1 Timer interrupt enabled Timer interrupt disabled
Description Default
*
TF: Timer Flag TF Read Write
Data 0 1 0 1 Timer flag inactive
Description Timer flag active. At the end of a timer countdown, TF is set to 1. Timer flag is cleared Timer flag remains unchanged
*
TI/TP: Timer Interrupt output select TI/TP Data 0
Description
INT is active when TF is active (subject to the status of TIE) INT pulses active according to source clock frequency and timer count down value (subject to the status of TIE).
Read / Write 1
Source clock (Hz) 4096 64 1 1/60
INT negative pulse width (s) n=1 n>1 1 1 /8192 /4096 1 1 /128 /64 1 1 /64 /64 1 1 /64 /64
Note: TF and INT become active simultaneously. n = loaded countdown value. Timer stopped when n = 0.
Example 1: If TE = 1, TD1 TD0 = 00, Timer = 03, TIE = 1, TF = 0, TI/TP = 1 are written into PT7C4363, timer register counts down every 1/4.096kHz seconds from 03 to 01 then 03 cycled and INT output negative pulse with 1/4096 seconds width. See Fig.1.
4.096kHz internal clock
Timer=02 Timer=01 Timer=03 Timer=02 Timer=01 Timer=03
Set TF=1
INT
Fig.1 Example 1 of timer interrupts
PT0207(07/05) 7
Ver: 0
Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Example 2: If TE = 1, TD1 TD0 = 10, Timer = 03, TIE = 1, TF = 0, TI/TP = 1 are written into PT7C4363, timer counts down every 1/4.096kHz seconds from 03 to 01 then 03 cycled and INT output negative pulse with 1/64 seconds width. See Fig.2.
1Hz internal clock
Timer=02 Timer=01 Timer=03 Timer=02
1/64
INT
Set TF=1
Fig.2 Example 2 of timer interrupts c) * Alarm Interrupt AIE: Alarm Interrupt Enable bit. AIE Data 0 Read / Write 1 * AF: Alarm Flag AF Read Write Alarm interrupt enabled Alarm interrupt disabled
Description Default
Data 0 1 0 1 Alarm flag inactive Alarm flag active Alarm flag is cleared Alarm flag remains unchanged
Description
d) *
SQW control SQWE: SQW output clock enable bit. SQWE Data 0 Read / Write 1 the SQW output is activated
Description
the SQW output is inhibited and SQW output is set to high-impedance Default
*
RS1, RS0: SQW output frequency select. RS1, RS0 Data 00 01 Read / Write 10 11 32 1 32.768k 1.024k
SQW output freq. (Hz) Default
PT0207(07/05) 8
Ver: 0
Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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e) *
Time count STOP STOP
Data 0 RTC source clock runs.
Description Default
Read / Write 1
All RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (SQW at 32.768 kHz is still available)
f) *
Test TEST1 TEST1 Read / Write 1 EXT_CLK test mode.
Data 0 Normal mode.
Description Default
*
TESTC TESTC Read / Write
Data 0 1
Description Power-on reset override facility is disabled; set to logic 0 for normal operation. Power-on reset override may be enabled Default
3.
Time Counter
Time digit display (in BCD code): * Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. * Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. * Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. (hex) 02 03 04 Description Seconds (default) Minutes (default) Hours (default) D7 OSF*1 1 x 0 x 0 D6 D5 D4 D3 D2 D1 D0
S40 S20 S10 S8 S4 S2 S1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined M40 M20 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined x 0 H20 H10 H8 H4 H2 H1 Undefined Undefined Undefined Undefined Undefined Undefined
*1 Note: Indicate clock integrity. When the bit is 1, the clock integrity is no longer guaranteed and the time need be adjusted.
PT0207(07/05) 9
Ver: 0
Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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4. Days of the week Counter The day counter is a divide-by-7 counter that counts from 00 to 06 and up 06 before starting again from 00. Values that correspond to the day of week are user defined but must be sequential (i.e., if 0 equals Sunday, then 1 equals Monday, and so on). Illogical time and date entries result in undefined operation. Addr. (hex) 06 Description Days of the week (default) Calendar Counter D7 x 0 D6 x 0 D5 x 0 D4 x 0 D3 x 0 D2 D1 D0
W4 W2 W1 Undefined Undefined Undefined
5.
The data format is BCD format. * Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. * Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. * Year digits: Range from 00 to 99 and 00, 04, 08, ... , 92 and 96 are counted as leap years. Addr. (hex) 05 07 08
Description Dates (default) Months (default) Years (default)
D7 x 0 Century*1 Undefined
D6 x 0 x 0
D5
D4
D3
D2
D1
D0
D20 D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Undefined x 0 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined
Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
*1: The century bit is toggled when the years register overflows from 99 to 00. 6. Alarm Register PT7C4363: Alarm Register Addr. 09 0A 0B 0C Description Alarm: Minutes (default) Alarm: Hours (default) Alarm: Dates (default) Alarm: Weekday (default) D7
*1
D6
D5 M20 Undefined H20 Undefined D20 Undefined x 0
D4
D3
D2
D1
D0
AE M40 Undefined Undefined AE*2 Undefined AE*3 Undefined AE*4 Undefined x 0 x 0 x 0
M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined H10 H8 H4 H2 H1 Undefined Undefined Undefined Undefined Undefined D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined x 0 x 0 W4 W2 W1 Undefined Undefined Undefined
*1 Note: Minute alarm enable bit. *2 Note: Hour alarm enable bit. *3 Note: Date alarm enable bit. *4 Note: Weekday alarm enable bit.
PT0207(07/05) 10
Ver: 0
Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Alarm Function
Related register Function 01 02 03 04 05 06 09 0A 0B 0C Control/status 2 Seconds Minutes Hours Dates Days of the week Alarm: Minutes Alarm: Hours Alarm: Dates Alarm: Weekday Bit 7 OSF x x x x AE AE AE AE Bit 6 S40 M40 x x x M40 x x x Bit 5 S20 M20 H20 D20 x M20 H20 D20 x Register definition Bit 4 Bit 3 TI/TP S10 M10 H10 D10 x M10 H10 D10 x AF S8 M8 H8 D8 x M8 H8 D8 x Bit 2 TF S4 M4 H4 D4 W4 M4 H4 D4 W4 Bit 1 AIE S2 M2 H2 D2 W2 M2 H2 D2 W2 Bit 0 TIE S1 M1 H1 D1 W1 M1 H1 D1 W1
When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable (AE) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AE at logic 1 will be ignored.
EXT_CLK Test Mode and POR override
1. EXT_CLK Test Mode A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit TEST1 in control/status1 register. Then pin SQW becomes an input. The test mode replaces the internal 64 Hz signal with the signal applied to pin SQW. Every 64 positive edges applied to pin SQW will then generate an increment of one second. The signal applied to pin SQW should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from SQW, is divided down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0 (STOP must be cleared before the pre-scaler can operate again). From a STOP condition, the first 1 second increment will take place after 32 positive edges on SQW. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the pre-scaler can be made.
PT0207(07/05) 11
Ver: 0
Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Operation example: 1. Set EXT_CLK test mode (control/status 1, bit TEST1 = 1) 2. Set STOP (control/status 1, bit STOP = 1) 3. Clear STOP (control/status 1, bit STOP = 0) 4. Set time registers to desired value 5. Apply 32 clock pulses to SQW 6. Read time registers to see the first change 7. Apply 64 clock pulses to SQW 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments. 2. Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the I2C-bus pins, SDA and SCL, be toggled in a specific order as shown in Fig 6.4.2. All timings are required minimums. Once the override mode has been entered, the device immediately stops being reset and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus access. The override mode may be cleared by writing a logic 0 to TESTC. TESTC must be set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal operation has no effect except to prevent from entering the POR override mode.
Power up
Override active
Fig.3 POR override sequence
PT0207(07/05) 12
Ver: 0
Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Communication
1. a) I2C Bus Interface Overview of I2C-BUS
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. b) System Configuration
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed).
Vcc RP RP
SDA SCL
Master MCU
Slave RTC
Other Peripheral Device
Note: When there is only one master, the MCU is ready for driving SCL to "H" and R P of SCL may not required.
Fig.4 System configuration
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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c)
Starting and Stopping I2C Bus Communications
Fig.5 Starting and stopping on I2C bus START condition, repeated START condition, and STOP condition * START condition SDA level changes from high to low while SCL is at high level * STOP condition SDA level changes from low to high while SCL is at high level * Repeated START condition (RESTART condition) In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. d) Data Transfers and Acknowledge Responses during I2C-BUS Communication
* Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. The address auto increment function operates during both write and read operations. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition.
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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* Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
1
2
8
9
SDA from transmitter (sending side)
Release SDA
SDA from receiver (receiving side)
Low active ACK signal
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a STOP condition from the Master. e) Slave Address
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. An R/W bit is added to each 7-bit slave address during 8-bit transfers. Operation Read Write Transfer data bit 7 A3 h A2 h 1 bit 6 0 bit 5 1 Slave address bit 4 0 bit 3 0 bit 2 0 bit 1 1 R / W bit bit 0 1 (= Read) 0 (= Write)
2.
I2C Bus's Basic Transfer Format
S
Start indication
P
Stop indication
A
RTC Acknowledge
Sr
Restart indication
A
Master Acknowledge
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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a)
Write via I2C bus
S 1
Start
Slave address (7 bits) 0 1 0 0 0 1
write
A
Addr. setting
A
bit
bit
bit
bit
bit
bit
bit
bit
0
A C K
7
6
5
4
3
2
1
0
A
P
Slave address + write specification
Address Specifies the write start address.
A C K
Write data
A C K
Stop
b) *
Read via I2C bus Standard read
S 1
Start
Slave address (7 bits) 0 1 0 0 0 1
write
A
Addr. setting
A
0
A C K
Slave address + write specification
Address Specifies the read start address.
A C K
Sr 1
Restart
Slave address (7 bits) 0 1 0 0 0 1
Read
A
bit
bit
bit
bit
bit
bit
bit
bit
1
A C K
7
6
5
4
3
2
1
0
A
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
/ A
N O A C K
P
Slave address + read specification
Data read (1) Data is read from the specified start address and address auto increment.
A C K
Data read (2) Address auto increment to set the address for the next data to be read.
Stop
*
Simplified read
S 1
Start
Slave address (7 bits) 0 1 0 0 0 1
Read
A
bit
bit
bit
bit
bit
bit
bit
bit
1
A C K
7
6
5
4
3
2
1
0
A
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
/ A
N O A C K
P
Slave address + read specification
Data read (1) Data is read from the address pointed by the internal address register and address auto increment.
A C K
Data read (2) Address register auto increment to set the address for the next data to be read.
Stop
Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. 2. 49H, 4AH are used as test mode address. Customer should not use the addresses.
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Maximum Ratings
Storage Temperature.......................................................................................................................-65oCto +150oC Ambient Temperature with Power Applied...........................................................................-40oCto +85oC Supply Voltage to Ground Potential (Vcc to GND) ..........................................................-0.3V to +6.5V DC Input (All Other Inputs except Vcc & GND)................................................................-0.3V to (Vcc+0.3V) DC Output Voltage (SDA, /INTA, /INTB pins)..................................................................-0.3V to +6.5V Power Dissipation............................................................................................................................320mW (Depend on package)
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Symbol VCC VIH VIL TA Power voltage Input high level Input low level Operating temperature Description Min 1.8 0.7 VCC -0.3 -40 Type Max 5.5 VCC+0.3 0.3 VCC 85 C V Unit
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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DC Electrical Characteristics
Unless otherwise specified, GND =0V, VCC = 1.8 ~ 5.5 V, TA = -40 C to +85 C, fOSC = 32.768kHz. Sym. Description Supply voltage VCC Supply voltage for clock data integrity Pin VCC VCC Interface active fSCL = 400kHz fSCL = 100kHz VCC = 5.0V VCC = 3.0V VCC = 2.0V VCC = 5.0V VCC = 3.0V VCC = 2.0V VCC = 5.0V VCC = 3.0V VCC = 2.0V VCC = 5.0V VCC = 3.0V VCC = 2.0V 0 0.7VCC -3 -1 Conditions Interface inactive. TA = 25C Interface active. fSCL = 400kHz 1)
1)
Min 1.0 1.8 1.0
Typ
Max 5.5 5.5
Unit
V
0.9 800 200 550 500 450 750 650 600 1600 1000 800 1700 1100 900 0.3VCC VCC A
ICC Supply current
VCC
Interface inactive (fSCL = 0Hz), pin 7 disabled 2)
TA = 25C
TA = -40 ~ 85C
Interface inactive (fSCL = 0Hz), pin 7 enabled at 32kHz 2) VIL1 Low-level input voltage VIH1 High-level input voltage IOL IIL IOZ Low-level output voltage Input leakage current Output current when OFF
TA = 25C
TA = -40 ~ 85C
275 250 225 500 400 400 825 550 425 950 650 500
nA
nA
nA
nA
SCL SCL SDA VOL = 0.4V, VCC = 5V /INT, SQW VOL = 0.4V, VCC = 5V SCL
V mA
1 1
A A
Note: 1) For reliable oscillator start-up at power-up: VCC(min)power-up = VCC(min) + 0.3 V. 2) Timer source clock = 1/60 Hz, voltage of SCL and SDA is VCC or GND.
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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AC Electrical Characteristics
Sym VHM VHL Description Rising and falling threshold voltage high Rising and falling threshold voltage low Value 0.8 VCC 0.2 VCC Unit V V
Signal VHM VLM
tf
tr
Over the operating range Symbol fSCL tSU;STA tHD;STA tSU;DAT tHD;DAT1 tHD;DAT2 tSU;STO tBUF tLOW tHIGH tr tf tSP* CB SCL clock frequency START condition set-up time START condition hold time Data set-up time (RTC read/write) Data hold time (RTC write) Data hold time (RTC read) STOP condition setup time Bus idle time between a START and STOP condition When SCL = "L" When SCL = "H" Rise time for SCL and SDA Fall time for SCL and SDA Allowable spike time on bus Capacitance load for each bus line Item Min. 0.6 0.6 200 35 0 0.6 1.3 1.3 0.6 0.3 0.3 50 400 Typ. Max. 400 Unit kHz s s ns ns s s s s s s s ns pF
* Note: Only reference for design.
S SCL tLOW fSCL tHIGH
Sr tHD;STA tSP
P
tSU;STA
tBUF
SDA tHD;STA tSU;DAT tHD;DAT tSU;STA tSU;STO tHD;STA
S Sr
Start condition Restart condition
P
Stop condition
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Mechanical Information
P/PE PDIP-8
8
.240 .280
6.09 7.11
1 .355 .400 9.01 10.16 7.62 8.25 .300 .325 .210 Max 5.33 SEATING PLANE .008 .014 0.20 0.35 .015 Min .115 .150 2.921 3.81 .100 typical 2.54 0.381 .430 Max 10.92
DENOTES DIMENSIONS IN MILLIMETERS
0O 15o
.014 .022
.356 .558
X.XX X.XX Note
1) Controlling dimensions in inches. 2) Ref: JDDEC MS-001 BA
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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W/WE SOIC-8
8 .0099 0.25 .0196 0.50 .149 3.78 .157 3.99 x 45o
0-8o 0.40 1.27 .016 .050
.0075 .0098
0.19 0.25
1 .189 .196 4.80 5.00
.2284 .2440 5.80 6.20
.016 .026 0.406 0.660 REF .050 BSC 1.27
.053 .068
1.35 1.75 SEATING PLANE
X.XX X.XX Note:
DENOTES DIMENSIONS IN MILLIMETERS
.0040 .0098 .013 0.330 .020 0.508
0.10 0.25
1) Controlling dimensions in millimeters. 2) Ref: JDDEC MS-012 AA
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Data Sheet PT7C4363 Real-time Clock Module (I2C Bus)
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Notes
Pericom Technology Inc.
Email: support@pti.com.cnWeb Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Asia Pacific:
U.S.A.:
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
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